There has been steady development of the semiconductor industry. The semiconductor industry is quantitatively and qualitatively improving to satisfy market and technology demands. Aspects of the semiconductor industry focus on minimization and integration of semiconductor transistors. Minimization and integration of semiconductor transistors may be accomplished by minimizing the size of elements included in semiconductor devices.
As semiconductor devices are fabricated at smaller sizes, larger amounts of devices may be integrated on a single chip. As a result, electrons may be able to pass through the devices more quickly, improving the processing speed of a semiconductor device. Additionally, the number of electrons that pass through a semiconductor may be reduced when the size of a semiconductor device reduces, reducing power consumption.
High integration, high speed, and low power consumption of the semiconductor device generally illustrate the historical performance improvements of semiconductor devices over time. In 1971, a minimum line width of a transistor was 10 μm. However, the minimum line width of the transistor improved to 0.25 μm in 1997 and to 90nm in 2003.
Over the past 30 years, semiconductor devices have improved in terms of size, degree of integration, and chip speed. For example, the size of semiconductor devices has generally reduced by a factor of about 50, the degree of integration has generally increased by a factor of about 10,000, and chip speed has generally improved by a factor of about 1000. Research has been conducted exhibiting a transistor having a line width of about 90 nm. Furthermore, transistors having a line width of about 65 nm are under development.
In 0.13-micron semiconductor manufacturing processes, a gate having a width of approximately 70 nm is formed in a wafer having a size of approximately 200 mm. In 90 nm semiconductor manufacturing processes, a gate having a width of approximately 50 nm can be formed in a wafer having a size of approximately 300 mm. In the future, it may be possible that a gate having a width of approximately 35 nm may be formed in a wafer of at least 300 mm through 65 nm semiconductor manufacturing processes. 90 nm semiconductor manufacturing processing exhibits various advantages compared to 0.13-micron semiconductor manufacturing processing. For example, a 1.2 nm gate oxide layer, a 50 nm gate layer, and a 50 nm strained silicon layer may be manufactured through 90 nm semiconductor manufacturing processing, may produce a high speed and low power consumption transistor. Additionally, since 90 nm semiconductor manufacturing processing may use 300 nm wafers, manufacturing costs may be reduced. It is possible that these developments in semiconductor processing will continue in the future.
One structure of a transistor is a MOSFET (metal oxide silicon field effect transistor) transistor. The basic operation of a transistor is based on a drift-diffusion equation. This basic operating principal has not changed, even as the size of semiconductor devices has been reduced by a factor of at least 50 over time. Accordingly, MOSFET technology fundamentals are projected to remain unchanged during the developing minimization of semiconductor devices. However, there are challenges that MOSFET devices face during fabrication of semiconductor devices having line widths of 0.1 μm or less (e.g. nano-scale semiconductor devices).
Technology for growing strained silicon has developed. When growing strained silicon, a germanium specimen is placed on a silicon substrate and heat may be applied to grow germanium (Ge) from the silicon substrate. Silicon (Si) may then be bonded to germanium (Ge) and heat may be applied to grow strained silicon. The strained silicon may have a grain size substantially the same as germanium (Ge).
The size of a semiconductor device employing strained silicon may be relatively small. However, mobility of electrons and holes may be lowered. Accordingly, there is a need for strained silicon MOSFET devices with adequate mobility of electrons and holes.
During fabrication of strained silicon MOSFET devices, germanium (Ge) may be grown from silicon (Si) such that the interval between silicon atoms is enlarged to correspond to the interval between germanium atoms. Silicon (Si) may then be grown to form strained silicon. The strained silicon may be used to form a strained silicon MOSFET to have a grid structure with spacing larger than that of silicon (Si).
FIG. 1 is an example graph illustrating an increase of electron mobility in a semiconductor device employing strained silicon. The y-axis represents the effective mobility of electrons and an x-axis represents the vertical effective field. A strained silicon semiconductor device, including silicon that is strained using silicon-germanium having about a 15% atom density of germanium (e.g. reference numeral 15), has a higher effective mobility compared to a semiconductor device without strained silicon (e.g. reference numeral 10). Likewise, a semiconductor device with silicon that is strained using silicon-germanium having about a 16% atom density of germanium (see, reference numeral 16), has more effective mobility.
In general, a vertical effective field for a semiconductor device may be in the range of 500 to 600K(V/Cm). For example, a silicon semiconductor device without strained silicon (e.g. represented by reference number 10) may exhibit electron mobility of about 270 Cm2/V0s. A semiconductor device having strained silicon using silicon-germanium having about 15% atom density of germanium may exhibit electron mobility of about 450 Cm2/V0s (e.g. see reference numeral 15). Likewise, a semiconductor device having strained silicon using silicon-germanium having about 16% atom density of germanium may exhibit electron mobility of about 480 Cm2/V0s (e.g. see reference numeral 16). Accordingly, when an active silicon layer is strained using a silicon-germanium epitaxial layer having about 16% atom density of germanium, electron mobility may be improved by about 70% or more.
Although semiconductor devices employing strained silicon may improve performance by increasing the mobility of electrons and holes, it cannot reduce DIBL (drain induced barrier lowing). DIBL in nano-scale semiconductor devices may be caused by leakage current and/or junction breakdown voltage.